ModelSim is a tool for simulation and verification for Verilog, VHDL and system Verilog. All the designs are compiled into the library and the user start the new design simulation in ModelSim by creating a library which is called work. Work is the default library name used by the compiler. Once the working library is created the next step is to compile the design units into it. The created library of ModelSim is compatible with all the platforms which means you can simulate your design in any platform.
Mentor Graphics was the first to combine single kernel simulator (SKS) technology with a unified debug environment for Verilog, VHDL, and SystemC. The combination of industry-leading, native SKS performance with the best integrated debug and analysis environment make ModelSim the simulator of choice for both ASIC and FPGA designs. The bes standards and platform support in the industry make it easy to adopt in the majority of process and tool flows.